The Optoboard is a PCB that hosts the ASICs to perform the (de-)multiplexing and the electrical-optical (optical-electrical) conversion. It is mounted with:
Picture credit: https://edms.cern.ch/ui/file/2379183/1/AT2_IP_MG_0010_v2.5.pdf
As seen in the figure above, the uplink signals from the ATLAS detector (up to 24 signals per Optoboard) are received by the GBCR (up to six signals per GBCR chip), recovered, and transmitted to the lpGBT where they are serialised and transmitted to the VTRx+ module. Here, the electrical signal is converted into optical and sent out through the optical cable plant, to the FELIX readout card. The downlink signals (up to eight electrical signals per Optoboard) will follow the opposite path from the FELIX card. They are sent via optical fibres (a single fibre per Optoboard) to the VTRx+ module, converted into electrical signals, parallelised and pre-emphasised in the lpGBT master chip and sent to the modules, bypassing the GBCR chips.
The power distribution of the Optoboxes (with multiple optoboards, typically 8) uses a two-stage DC/DC converter system, composed of bPOL12V and bPOL2V5 converters. The main supply is provided at 9 V and is adapted to 2.5 V by the bPOL12V converter. The 2.5 V supply powers the VCSEL driver of the VTRx+ module and the bPOL2V5. This second converter provides the 1.2 V voltage used by the ASICs on the Optoboard. The bPOL12V chips are mounted, in groups of five, on a PCB called Powerboard. Their power is distributed to up to eight Optoboards by the Connector board.
Resources:
Optoboard system documentation - https://optoboard-system.docs.cern.ch/
Talk on "Optoboard Development for Inner Tracker of High Luminosity ATLAS Detector" (https://indico.cern.ch/event/716246/contributions/3049845/attachments/1707958/2752462/Optoboard_Development_Armin_Fehr_SPS_2018.pdf)
SLAC setup (https://confluence.slac.stanford.edu/pages/viewpage.action?pageId=353752832)
Optobox interfacs (https://edms.cern.ch/ui/#!master/navigator/document?D:100639026:100639026:subDocs)
GBCR2 has seven upstream receiver channels, two downstream transmitter channels, an I2C slave module, and a phase shifter. The seven upstream channels receive the data from the pixel modules through a flex and a twinax cable directly and send the recovered signals to lpGBT.
Resources: Manual (https://edms.cern.ch/ui/#!master/navigator/document?P:100324489:100646067:subDocs)
The Low Power Giga Bit Transceiver (lpGBT) is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics experiments. The ASIC supports 2.56 Gb/s links in the direction from the counting room to the detectors (downlink) and 5.12 or 10.24 Gb/s links in the direction of the detectors to the counting room (uplink), depending on the selected operation mode.
Resources: Manual (https://cds.cern.ch/record/2809058/files/lpGBT_manual.pdf)
The front-end module (VTRx+) will be based on radiation-hard laser diode driver (LDD) and transimpedance amplifier (TIA) ASICs, and commercial VCSEL and PIN photodiode (PD) components. A set of passive components (optical fibre and connectors) will connect the VTRx+ to the off-detector electronics where Commercial Off-The-Shelf (COTS) optical transmitter and receivers will provide the interface to FPGAs. The VL+ is designed to operate together with the lpGBT Serializer/Deserializer (SerDes), although other SerDes types can be supported. The target operating data-rates for the VL+ are set by the lpGBT: 2.56 Gb/s in the downstream towards the detector; and 5.12 or 10.24 Gb/s in the upstream away from the detector.
Resources:
PoS TWEPP2019 (https://espace.cern.ch/project-Versatile-Link-Plus/Shared Documents/Publications/2019_Olantera_PoS(TWEPP2019)055.pdf)
PoS TWEPP2017 (https://inspirehep.net/files/f2b8685027fa468a7e4d3a6514a3416c)
EDMS (https://edms.cern.ch/ui/#!master/navigator/project?P:1484090842:1484090842:subDocs)
Technical specification (https://edms.cern.ch/ui/#!master/navigator/document?D:1989550282:1989550282:subDocs)
FELIX is a new detector readout component developed as part of the ATLAS upgrade effort. FELIX is designed to act as a data router, receiving packets from detector front-end electronics and sending them to programmable peers on a commodity high bandwidth network. Whereas previous detector readout implementations relied on diverse custom hardware platforms, the idea behind FELIX is to unify all readout across one well supported and flexible platform. Rather than the previous hardware implementations, detector data processing will instead be implemented in software hosted by commodity server systems subscribed to FELIX data. From a network perspective FELIX is designed to be flexible enough to support multiple technologies, including Ethernet and Infiniband.
Resources:
Paper (https://arxiv.org/abs/1806.10667)
User manual (https://atlas-project-felix.web.cern.ch/atlas-project-felix/user/felix-doc/-/felix-user-manual/Latest/felix-user-manual/Latest/felix-user-manual.html)
PDR of the TDAQ Phase-II Readout using FELIX (https://indico.cern.ch/event/1108368/)
ATLAS FELIX project (https://atlas-project-felix.web.cern.ch/atlas-project-felix/)
SLAC setup (https://confluence.slac.stanford.edu/display/Atlas/FELIX+Readout#FELIXReadout-LpGBTBoardSpecificSetups)
RD53a Readout with FELIX (https://cds.cern.ch/record/2690124/)
Pin-to-pin Mapping between PP0 and the FELIX card connectors in the Data Transmission Chain for the ATLAS ITk Pixel Detector (https://edms.cern.ch/ui/#!master/navigator/document?P:100324489:101065941:subDocs)
General resources: